1. Field of the Invention
This invention relates to the field of high speed digital communications and in particular to mechanisms for high speed inter-processor communication.
2. Description of the Relevant Art
Improving technology fuels the drive to operate devices at higher frequencies. One of the problems encountered as a result of the use of higher frequencies for inter-processor communication is that of data skew. In connecting elements of a computer board such as processors, memory chips, and exterior interface ports, board designers must take into account the clock frequency and propagation delays of the data bus. At clock frequencies of 1 GHz a length difference of one centimeter between bus lines is sufficient to cause substantial misalignment in data which may result in bit errors when sampled according to a fixed clock signal. Hence the board designer must take great care to ensure that all data lines in the bus are of nearly the same length, which often requires the addition of otherwise unnecessary meanders to increase the length of shorter bus lines. When this is done, it does not necessarily eliminate all of the data skew, but it does create a "window" in which all the data signals are valid at the same time. This allows for the adjustment of the timing of the clock signal to line up with the window of data validity. As the number of bus lines increases, it becomes more difficult to create a window in which all data signals are valid, particularly since the length discrepancy grows with the width of the data bus. Bus widths of greater than 8 data lines often prove impractical due to the increase in area and layout complexity required by meanders. Consequently increasing bus widths or clock speeds are typically not methods which can be used to increase I/O throughput.
This being said, it is nevertheless the case that as processors increase in power and speed, the requirement for I/O throughput increases as well. This problem has been mainly addressed by using memory caching techniques to increase I/O efficiency. This is achieved by passing data in blocks rather than as individual bytes on the established pattern that memory accesses are not independent. Rather, they exhibit characteristics known as time-and-space locality which in effect means that when one memory location in a region is accessed, a high probability exists that subsequent memory accesses will be in the same region. By "gambling" on this and sending all the memory in the region along with the requested data byte, often the subsequent memory accesses can be eliminated since the processor already has the needed data. This increases the effective I/O throughput by a strategy which usually, but not always, works. It should be noted that this strategy does not exclude other approaches to increasing throughput, and can be used in conjunction with increases in clock speed and bus width if the data skew problem can be pragmatically overcome.